1. Field
Embodiments described herein relate generally to a semiconductor memory device.
2. Description of the Related Art
In recent years, resistance varying memories using a variable resistance element as a memory element are attracting attention as a candidate to succeed flash memories. Resistance varying memories include: a resistance varying memory in the narrowly-defined meaning (ReRAM: Resistive RAM), which stores, in a nonvolatile manner, a resistance state of its recording layer made of a transition metal oxide; a phase change memory (PCRAM: Phase Change RAM) which uses chalcogenide, etc. as its recording layer and utilizes the resistance information of the chalcogenide in its crystalline state (conductive) and its amorphous state (insulative), etc.
It is known that memory cells of the resistance varying memories have two types of operation modes. One is called bipolar type which sets a high resistance state and a low resistance state by switching the polarities of voltages to apply. The other is called unipolar type which enables to set a high resistance state and a low resistance state not by switching the polarities of voltages to apply but by controlling voltage values and voltage application times.
The unipolar type is preferred in order to realize a high-density memory cell array, because when the unipolar type is used, it is possible to configure a cell array not by using a transistor but by stacking a variable resistance element and a rectifying element such as a diode, etc. at the intersections of bit lines and word lines. Furthermore, by stacking such memory cell arrays three-dimensionally, it is possible to realize a large memory capacity without increasing the cell array area.
When assembling a three-dimensional memory cell array in a resistance varying memory, bit lines are formed in plural layers in the stacking direction, and word lines are formed in plural layers in the stacking direction such that the word lines intersect the bit lines. The memory cell array is formed with memory cells formed three-dimensionally at the intersections of the bit lines and the word lines. Control circuits for controlling the voltages of the bit lines and the word lines are formed on a semiconductor substrate under the memory cell array. The issue of the device having the above configuration is to form a wiring configuration with accuracy and supply desired voltages to the memory cells.